Broadcom has announced a significant breakthrough in AI computing with its new 3.5D eXtreme Dimension System in Package (XDSiP) platform. This innovative technology empowers developers to create next-generation custom accelerators, known as XPUs, designed to handle the immense computational demands of advanced artificial intelligence applications. The XDSiP platform represents a monumental leap in chip integration, packing over 6000 mm² of silicon and up to 12 high-bandwidth memory (HBM) stacks into a single package. This unprecedented density translates to remarkably high-efficiency, low-power computing, crucial for scaling AI operations effectively.
Broadcom’s achievement is particularly noteworthy in its development and launch of the industry’s first Face-to-Face (F2F) 3.5D XPU. This milestone directly addresses the challenges posed by the exponential growth in AI model complexity. Training generative AI models, for instance, requires massive clusters – from 100,000 to potentially 1 million – of XPUs. These XPUs require sophisticated integration of compute power, memory, and I/O capabilities, all while striving for optimal performance, minimal power consumption, and cost-effectiveness. Traditional approaches like relying solely on Moore’s Law and process scaling are falling short of meeting this demand. This is where Broadcom’s advanced system-in-package (SiP) integration becomes critically important for the future of AI.
Broadcom highlights the evolution of packaging technology. Over the past decade, 2.5D integration has proven valuable, integrating multiple chiplets up to 2500 mm² of silicon and up to 8 HBMs on an interposer. However, the advent of increasingly complex large language models (LLMs) necessitates a more advanced solution. The company argues that 3.5D integration – combining 3D silicon stacking with 2.5D packaging – is poised to dominate the next generation of XPUs, providing crucial advantages in size, power efficiency, and cost.
Key Benefits and Industry Collaboration:
Frank Ostojic, Senior Vice President and General Manager, ASIC Products Division at Broadcom, emphasizes the crucial role of advanced packaging in overcoming the limitations of Moore’s Law in next-generation XPU clusters. The company’s 3.5D XDSiP platform leverages technology and tools from partners like TSMC and EDA companies. The vertical stacking of chip components enables pairing of optimal fabrication processes for each component, leading to significant reductions in interposer and package size. This results in dramatic improvements in performance, efficiency, and cost reduction.
Dr. Kevin Zhang, Senior Vice President of Business Development & Global Sales and Deputy Co-COO at Taiwan Semiconductor Manufacturing Company (TSMC), underscores the close collaboration between TSMC and Broadcom. This collaboration blends TSMC’s advanced logic processes and 3D chip stacking technologies with Broadcom’s design expertise. The companies are focused on productizing this platform to drive AI innovation and future growth.
Naoki Shinjo, SVP and Head of Advanced Technology Development at Fujitsu, highlights the long-standing partnership with Broadcom, which has successfully brought multiple generations of high-performance computing ASICs to market. Broadcom’s 3.5D platform is enabling Fujitsu’s next-generation 2-nanometer Arm-based processor, FUJITSU-MONAKA, to achieve exceptional performance with low power consumption and reduced costs.
Broadcom’s 3.5D XDSiP platform signifies a major leap forward in AI computing, paving the way for more powerful, efficient, and cost-effective AI solutions that can handle the increasingly complex demands of the future. The industry collaboration showcased by this announcement underscores the collective effort to push the boundaries of what’s possible in AI technology.
