AMD’s new Ryzen AI 300 series ‘Strix Point’ APUs, featuring the latest Zen 5 architecture, are now finding their way into Copilot+ AI systems. We now have our first detailed die shot of the Strix Point APU, offering a glimpse into its intricate design. The Zen 5-based Strix Point APU die stands out as larger than its predecessor, the Zen 4-based Phoenix APU. Measuring 12.06 mm x 18.71 mm (L x W), it surpasses the Phoenix’s 9.06 mm x 15.01 mm. This larger footprint is attributed to the inclusion of a bigger CPU (Zen 5), a more robust integrated GPU (RDNA 3.5), and a more substantial NPU (XDNA 2). AMD has opted for the improved TSMC N4P process node for the Strix Point APU, a step up from the N4 process node used for its Phoenix and Hawk Point APUs. Nemez (GPUsAreMagic) has meticulously annotated the die shot, providing a comprehensive understanding of its intricate components.
AMD’s Strix Point APU boasts up to 12 cores distributed across two CCXs. One CCX houses 4 x Zen 5 cores, sharing a 16MB L3 cache, while the other features 8 x Zen 5c cores with an 8MB L3 cache. These CCXs are interconnected through the Infinity Fabric, facilitating seamless communication. The new RDNA 3.5-based integrated GPU occupies a prominent central space on the die, demonstrating its significance. This GPU incorporates 8 workgroup processors (WGPs), equivalent to 16 Compute Units and 1024 stream processors, delivering enhanced graphical capabilities. Other noteworthy components include 4 render backends, translating to 16 ROPs, and control logic. The RDNA 3.5 GPU has its own dedicated 2MB L2 cache, streamlining data transfers via the Infinity Fabric.
Strix Point is equipped with a second-generation XDNA 2-based NPU, significantly larger than the XDNA-based NPU found in the Phoenix. It features 32 AI engine tiles, interacting with its own high-speed local memory and a control logic interface connected to the Infinity Fabric. AMD is leveraging the XDNA 2-based NPU within its Ryzen AI 300 series ‘Strix Point’ APUs to deliver a remarkable 50 TOPS of AI workload performance. Moving on to the memory controller, Strix Point supports dual-channel (160-bit) DDR5 memory at native DDR5-5600 speeds and 128-bit LPDDR5-7500 memory. The memory controller incorporates an unspecified amount of SRAM cache, as noted by Nemez, who observed its presence in ‘Phoenix 2’ and ‘Phoenix’ dies but not in the cIOD of ‘Raphael’ and ‘Dragon Range’ chips.
