SK hynix has announced its plans to develop 4F2 (square) DRAM, joining its South Korean rival Samsung in the pursuit of 3D DRAM technology. This move comes in response to the escalating costs of extreme ultraviolet (EUV) lithography processes, which have skyrocketed since the commercialization of 1c DRAM.
During an industry conference in Seoul, SK hynix researcher Seo Jae Wook acknowledged the rising costs associated with EUV processes and the need to find more cost-effective solutions for future DRAM production.
SK hynix’s 4F2, internally referred to as vertical gate (VG) DRAM, is a 3D cell array structure where the transistors are stacked vertically. This vertical stacking approach, also known as 3D DRAM, includes the vertical alignment of the source, gate, drain, and capacitor, with the word line connected to the gate and the bit line connected to the source.
The 4F2 architecture offers a significant advantage by reducing the die surface area by 30% compared to traditional 6F2 DRAM. Industry sources indicate that both Samsung and SK hynix are aiming to utilize 4F2 for DRAM production at the 10nm node and below.
SK hynix’s Seo highlighted the potential of 4F2 (VG or 3D DRAM) to reduce EUV process costs by half, making it a crucial development for the future of DRAM manufacturing. This cost reduction could significantly improve the efficiency and profitability of DRAM production while enabling the creation of more advanced and powerful memory chips.
